/*----------------------------------------------------------------------
 *
 * testbench description here
 *
 * NOTE : this is a fairly simple test bench and you should consider
 * setting up a test harness and using that instead.
 *
 *---------------------------------------------------------------------*/


module s3board_test ();

  parameter TESTBENCH_TIMEOUTus = 30000;
  parameter TEST_NAME = "s3board_test";

  //----------------------------------------
  reg                 clk50;

  reg [3:0]           btn;
  reg [7:0]           swt;
  wire [3:0]          an;
  wire [7:0]          ssd;
  wire [7:0]          led;
  //----------------------------------------

  //----------------------------------------
  // serial ports
  reg                 txd_in;
  wire                rxd_out;

  reg                 aux_txd_in;
  wire                aux_rxd_out;
  //----------------------------------------


  /*----------------------------------------------------------------*/

  /*AUTOREG*/

  /*AUTOWIRE*/

  /*------------------------------------------------------------------
   *
   * local definitions and connections.
   *
   * */

`include "dcom_apb_tasks.vh"

  /*-----------------------------------------------------------------
   *
   *
   *
   * */

  initial begin
    $display("module name = %s", TEST_NAME);
    $display("vzd file name = %s",{TEST_NAME,".netlist_vzd"});
  end

  initial begin
`ifdef VCD
 `ifdef NETLIST_SIM
  `ifdef VZD
    $dumpfile({TEST_NAME,".netlist_vzd"});
  `else
    $dumpfile({TEST_NAME,".netlist_vcd"});
  `endif
 `else
  `ifdef VZD
    $dumpfile({TEST_NAME,".vzd"});
  `else
    $dumpfile({TEST_NAME,".vcd"});
  `endif
 `endif
    $dumpvars(0);
    // $dumpvars(1, harness);
    // $dumpvars(1, harness.dut);
    // $dumpvars(0, harness.dut.digital_live_inst);
    // $dumpvars(0, harness.dut.digital_inst);
`endif
  end

  integer              timeout;
  initial begin
    for (timeout=0 ; timeout < TESTBENCH_TIMEOUTus; timeout=timeout+1) #1000;
    $display("*** ERROR - tesbench timeout at %t.", $time);
    $finish();
  end

  /*------------------------------------------------------------------
   *
   *
   *
   * */

  // 50MHz clk50.
  initial clk50 = 1'd0;
  always #10 clk50 <= ~clk50;

  /*-----------------------------------------------------------------
   *
   *
   *
   * */

  integer i;
  reg [31:0] data, expected_data;
  initial begin
    btn = 4'd0;
    swt = $random;
    txd_in = 1'd1;
    aux_txd_in = 1'd1;

    for (i=0 ; i<300; i=i+1) @ (posedge clk50);

    uart_write(3, 16'h0002);
    uart_read(3, data);
    $display("// got data 0x%x.", data);
    uart_write(3, 16'h0020);
    uart_read(3, data);
    $display("// got data 0x%x.", data);
    uart_write(3, 16'h0200);
    uart_read(3, data);
    $display("// got data 0x%x.", data);
    uart_write(3, 16'h2000);
    uart_read(3, data);
    $display("// got data 0x%x.", data);
    $finish();

    for (i=0 ; i<10; i=i+1) begin
      expected_data = $random;
      uart_write(2, expected_data);
      uart_read(2, data);
      if (expected_data != data) begin
        $display("*** ERROR - expected data 0x%2x, got 0x%2x.", expected_data, data);
        $finish();
      end else begin
        $display("// got expected data 0x%2x.", data);
      end
    end
    $finish();
  end

  /*-----------------------------------------------------------------
   *
   *
   *
   * */

  s3board dut
    (/*AUTOINST*/
     // Outputs
     .an                                (an[3:0]),
     .ssd                               (ssd[7:0]),
     .led                               (led[7:0]),
     .rxd_out                           (rxd_out),
     .aux_rxd_out                       (aux_rxd_out),
     // Inputs
     .clk50                             (clk50),
     .btn                               (btn[3:0]),
     .swt                               (swt[7:0]),
     .txd_in                            (txd_in),
     .aux_txd_in                        (aux_txd_in));

  /*----------------------------------------------------------------*/

endmodule // s3board_test


// Local Variables:
// verilog-library-directories:("." "../../modules/*")
// verilog-library-extensions:(".v")
// End:
